The invention relates to analog-to-digital conversion.
In typical analog-to-digital conversion, a reference voltage level is used to generate a digital representation of an analog input signal. Signal resolution is often maximized when the expected range of the analog input signal matches the reference voltage level. However, quite often the input signal to be converted has a much lower voltage level than the reference voltage level.
For example, an output of a CMOS image sensor may have a relatively low voltage level (as compared to the reference voltage level) due to a low light condition or operation at a high frame rate.
Performance from an analog-to-digital converter (ADC) may sometimes be increased by amplifying the output of the CMOS sensor to provide a stronger analog input signal to the ADC. Also, because signal strengths may vary with the environment or operating conditions of the sensor, it may be desirable for the amplifier to have a variable gain to accomodate these variations.
FIG. 1 shows a switched capacitor integrator 10 which may be used to amplify an output (represented by a sampled voltage called Vin*) of the sensor before A/D conversion. The integrator 10 uses complementary nonoverlapping clock signals to control on/off switches 17, 18 and 20 to transfer charge through capacitors 14 and 16 of the integrator 10. The capacitor 14 (typically the larger of the two capacitors) is connected in a feedback path between an inverting input and an output of an operational amplifier 12. The switch 20 selectively shorts across the capacitor 14 when connecting the output of the amplifier 12 to the inverting input.
The capacitor 16 has one terminal receiving the sampled input voltage Vin*. Another terminal of the capacitor 16 is alternatively connected (by the switches 17 and 18) between a reference voltage level V+ and an input terminal of the amplifier 12. The gain of the integrator 10 is ideally proportional to the ratio between the capacitances of the capacitors 14 and 16.
FIG. 2 shows another type of analog-to-digital converter 24 which uses a technique known as successive approximation. In this technique, a digital representation (called D.sub.-- OUT[7:0]) of the sampled voltage Vin* is derived by a sequence of structured estimates, or guesses. Each guess is represented by a multi-bit signal called GUESS[7:0] and is formed from the voltage Vin* by control logic 26. To evaluate the accuracy of each guess, the converter 24 has a comparator 30 (which furnishes an output called OUT). A digital-to-analog converter (DAC) 28 is used to convert the digital signal GUESS[7:0] into its analog equivalent (called VIN.sub.-- GUESS) for comparison by the comparator 30 with the voltage Vin*. Typically, one bit is tested (i.e., one guess is performed) during each step of the sequence. Thus, the number of guesses (and clock cycles) required to generate the digital representation DOUT[7:0] is equal to the number of bits of the representation. For example, the converter 24 spends eight clock cycles generating the eight bit representation D.sub.-- OUT[7:0].
FIG. 3 shows an example of a successive approximation sequence. The control logic 26 might be configured to start with the most significant bit of D.sub.-- OUT[7:0] (i.e., D.sub.-- OUT[7]) and process the bits of D.sub.-- OUT[7:0] in descending order. For example, assuming the correct value of D.sub.-- OUT[7:0] is "b01100001" (wherein the prefix "b" indicates a binary representation), the first guess might be "b10000000" to test the most significant bit of D.sub.-- OUT[7:0]. In response to this guess, the comparator 30 drives its output (represented by OUT) high. This indicates to the control logic 26 that the guess was higher than the actual value. As a result, the control logic 26 knows that the most significant bit of D.sub.-- OUT[7:0] has a logic zero level.
The control logic 26 then tests the value of the next significant bit (D.sub.-- OUT[6]) by guessing "b01000000." In response to this guess, the comparator 30 drives its output low which indicates to the control logic 26 that the guess was lower than the actual value. Because the control logic 26 knows that the most significant bit (D.sub.-- OUT[7]) has a logic zero level, the control logic 26 then deduces that the bit D.sub.-- OUT[6] must have a logic one level, and it follows, that one or more of the bits D.sub.-- OUT[5:0] have a logic one level. The control logic 26 then tests the next most significant bit (D.sub.-- OUT[5]) by guessing "b01100000," and the sequence continues until the logic levels of all bits of the representation D.sub.-- OUT[7:0] have been determined.